Field of the Invention
The present invention relates generally to the field of nonvolatile memory (NVM) devices. More particularly, the present invention relates to a single-poly NVM cell structure with an assistant gate (AG) and NVM array thereof.
Description of the Prior Art
Non-volatile memory devices, such as EEPROM and flash memory, are widely used in electronic devices to store data that can be electrically erased and reprogrammed and that must be saved when power is removed. Generally, NVM devices may be divided into multi-time programmable (MTP) memory and one-time programmable (OTP) memory. MTP memory is multi-readable and multi-writable. For example, EEPROM and flash memory are designedly equipped with some corresponding electric circuits to support different operations such as programming, erasing and reading. OTP functions perfectly with electric circuits with mere programming and reading functions. Electric circuits for erasing operation are not required in OTP.
Single-poly NVM designs have been proposed which reduce the additional processing cost. A single-poly NVM forms the charge-storage floating gate with a single layer of polysilicon. Because the single-poly NVM is compatible with regular CMOS process, it is applied in the field of embedded memory, embedded nonvolatile memory in the mixed-mode circuits and micro-controllers (such as System on Chip, SOC), for example.
It is known that programming of memory cell can be accomplished by hot electron injection techniques (also known as channel hot electron or CHE programming). Leakage current during programming and verification operations is exacerbated as the core device length is reduced. Moreover, as flash memory devices are scaled down and the channel length of the memory cells is reduced, program disturbs of adjacent devices also increase. Program disturb may occur in adjacent memory cells that share the same word line as the memory cell being programmed. Further, as dimensions and tunneling oxide of the memory cell unit continue to shrink, the data retention loss or charge leakage from the floating gate looms as an increasingly serious problem. Therefore, there is a strong need in this industry to improve the data retention or endurance characteristics of the NVM cell structure.